With the development of communication techniques, digital signal processing, and computer networking, the requirements of interfacing between analog and digital domains is increasing dramatically. High-speed, high-accuracy digital-to-analog converter (DAC) or analog-to-digital converters (ADC) are in great demand.
In DAC design, current mode converters are popular for use with video frequency or higher applications. Current-steering DACs are based on current cells arranged by binary weighted or thermometer code. Matching is critical for obtaining high accuracy. Many available CMOS digital processes are difficult if not impossible to achieve more than 10-bit matching accuracy. In order to achieve high accuracy, various calibration techniques have to be applied.
As described in Redfern et al., xe2x80x9cA Monolithic Charge-Balancing Successive Approximation A/D Technique,xe2x80x9d IEEE JSSC, Vol. SC-14, No. 6, pp. 912-920 (December 1979), which is incorporated herein by reference, one early calibration method utilized was laser trimming of thin film resistors. Accurate resistor values and exact matching can be achieved. The laser trimming, however, can cause thermal and mechanical stress, and the trimmed parts are sensitive to temperature and aging effects.
Techniques developed that allowed the conversion operation to calibrate itself (known as xe2x80x9cself-calibrationxe2x80x9d ) emerged as an alternative to laser trimming. One such technique, non-continuous self-calibration (also known as xe2x80x9cself-compensationxe2x80x9d), is a calibration procedure used in conversion systems and operations that are not continuously in use. A typical implementation of a non-continuous self-calibration technique is described in detail in Maio et al., xe2x80x9cAn Untrimmed D/A Converter with 14-bit Resolution,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 16, pp. 616-621 (December 1981), which is incorporated herein by reference. As part of the calibration phase, an accurate (reference) ramp signal is generated and the DAC output is compared to the reference ramp signal. The difference between the DAC output and the ideal output is detected during the calibration phase and used to compensate the DAC output issued during an actual conversion operation.
Continuous self-calibration is more efficient in that the overall conversion operation is continually performed without interruption by the calibration procedure. A typical implementation of a known continuous self-calibration technique in a current steering DAC based on dynamic element matching is illustrated in FIG. 7. As illustrated in FIG. 7, an N+1 shift register and N+1 current sources are provided for an n-bit conversion operation. One of the N+1 current sources is utilized as a spare source, as only N sources are needed to perform the conversion operation. At any given time, only one of the registers in the N+1 shift register has a value of xe2x80x9c1,xe2x80x9d the remaining registers having a value of xe2x80x9c0.xe2x80x9d Because the N+1 shift register selects the current source (or cell) to be calibrated, only one current cell is calibrated at a given time. Each current cell is individually calibrated to a reference current. When a selected cell is being calibrated, the xe2x80x9csparexe2x80x9d source effectively replaces the selected cell in the conversion operation and supplies output current in its place. A switching network is provided to perform the necessary switching functions needed to accomplish the calibration and conversion operations simultaneously.
The continuous self-calibration technique is commonly implemented in CMOS technology. Matching is not a major concern due to the dynamic element matching principle utilized in the calibration procedure. Signal glitching is evident during switching from a calibration mode to an output mode of the calibrated cells. Such signal glitching, however, can be ignored if the energy is less than xc2xd the least significant bit (LSB), as is the case in audio frequency applications where settling time is long enough. In high-speed applications (e.g., hundreds of MHz required in wireless personal communications, video signal processing, GHz LAN applications, etc.), however, the settling time (e.g., 1/Frequency of signal (Fs)) for the converted analog signal is short and the need for accuracy (e.g., more than 10-bit accuracy) is greater. In such applications, the signal glitches cannot only be higher than xc2xd LSB energy, but also cause unsettled results, leading to distortion. As a result, periodic errors with a frequency of the calibration clock exist that causes increased noise floor and deterioration of spurious free dynamic range (SFDR) of the converter. An illustration of a typical signal glitch occurring in known conversion operations is shown in the encircled portion 60 of FIG. 6.
In accordance with a preferred embodiment, a self-calibrated cell (and corresponding operation) is provided that receives a reference parameter (e.g., current, voltage, etc.) for storage in the cell and for supplying to a load. The individual cell is controlled to operate in different states or modes: either a redundant mode or a supplying mode. In the redundant mode, the reference parameter is stored in the current cell during a calibration phase or mode, and the stored reference parameter is dumped or otherwise transferred, preferably to ground, during a dumping state or mode. In the supplying mode, the current cell transfers or supplies the stored reference parameter to the load. The individual cell is controlled to operate in its dumping state both before the cell enters the calibration mode and also at the same time that the cell is switched from the calibration mode to the supplying mode. In accordance with a preferred embodiment, the individual cells may be employed in a cell array of a converter (e.g., digital-to-analog converter). All of the cells in the array may individually be placed in a redundant mode in succession, while the remaining cells are in a supplying mode.